dp

simCPU

This project simulates the complexity of a CISC processor.

At the beginning we will discuss the
Central Processing unit (CPU)

A CPU has to load addresses and / or data out of memory and execute operations. CPUs contain an Arithmetic Logical Unit (ALU), a Control Unit (CU) and some other components (see Fig. 1 (c) by Dr. J. Wolkerstorfer. Lecture 2, summer term 06). CPUs have access to memory and control I/O devices (see Fig. 2 (c) by Dr. J. Wolkerstorfer. Lecture 2, summer term 06).

A CPU executes operations in 5 parts, also called fetch and execute.

Fetch contains:

  • read instruction
  • decode instruction
  • read operand

Execute contains:

  • execute operation
  • store result

Now we will discuss
CISC, RISC and their differences

CISC = Complex Instruction Set Computing.
RISC = Reduced Instruction Set Computing.

All Pentium CPUs have CISC processors. You can see the format of an Pentium instruction in Fig. 3(c) by Dr. J. Wolkerstorfer Lecture 6, summer term 06. RISC processors are used in PICs, Sparcs etc. The format of RISC instructions are displayed in Fig. 4(c) by Dr. J. Wolkerstorfer Lecture 7, summer term 06.

Comparing Fig. 3 (c) by Dr. J. Wolkerstorfer Lecture 6, summer term 06. with Fig. 4 (c) by Dr. J. Wolkerstorfer Lecture 7, summer term 06, we can see that CISC is much more complex than RISC. CISC instructions vary from one to 16 bytes. Based on this fact, it’s obviously that a Control Unit in a CISC-based CPU has a little bit more to do than a Control Unit in a RISC-based CPU.

On the next page we will present the implementation…


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